1. Field of the Invention
The present invention relates to a method of lateral etching via holes for fabricating semiconductor devices. It finds a beneficial application in high performance CMOS semiconductor devices for fast signal processing and/or low-voltage/low-power applications, and more particularly in MOS field-effect transistors (MOSFET).
2. Description of the Related Art
One limiting factor of standard massive architecture MOSFETs is the substrate effect which degrades the performance of the transistor. This drawback is avoided in silicon on insulator (SOI) architecture MOSFETs by separating the thin film of silicon from the substrate by a buried layer of silicon oxide.
Eliminating the substrate effect in thin-film SOI architecture MOSFETs that are totally depleted increases the drain current.
However, ultrathin SOI architecture MOSFETs have a high source/drain (S/D) resistance because of shallow junctions limited by the thickness of the silicon layer and poor thermal conductivity. The cost of fabricating SOI architecture substrates is also high, which has restricted their entry into the market.
Silicon on nothing (SON) architecture semiconductor devices combining the advantages of the solid and silicon on insulation (SOI) architectures have been proposed to remedy the drawbacks of the above SOI or solid architecture devices. These semiconductor devices, such as an MOS field-effect transistor, feature extremely thin silicon films and buried oxides, i.e., a thickness on the order of a few nanometers.
FIG. 1 shows a SON architecture device of the above kind in which the buried dielectric layer is limited to the area underlying the gate region of the device.
Referring to FIG. 1, the semiconductor device comprises a silicon substrate 1. having a top surface coated with a thin gate dielectric layer 4 in which are formed source and drain regions 5 and 6. Source and drain regions 5 and 6 define between them a channel region 1a of predetermined minimum length and a gate 7 on the top surface of the body over the channel region 1a. The device further includes a continuous or discontinuous insulative cavity 2 in the channel region 1a between the source and drain regions 5 and 6. The insulating cavity 2 delimits, in conjunction with the source and drain regions 5 and 6, a thin silicon layer 3 from 1 nm to 50 nm thick overlying the insulative cavity 2. The insulative cavity has a length representing at least 70% of the predetermined minimum length of the channel region 1a. The gate 7 is flanked by spacers 8 and 9. Contacts 10, 11 are provided on the source and drain regions 5, 6.
The terms xe2x80x9ccavityxe2x80x9d and xe2x80x9ctunnelxe2x80x9d are used interchangeably hereinafter.
In the device described above the expression xe2x80x9cpredetermined minimum lengthxe2x80x9d of the channel region refers to the shortest channel length which can be used in a device of a given technology.
The insulative cavity can consist of any appropriate solid or gaseous dielectric material but is preferably a cavity filled with air.
A method of fabricating a semiconductor device may include:
forming, on a top surface of a silicon substrate 1, a layer of a material which can be selectively eliminated and which preferably ensures lattice continuity with the silicon substrate 1;
forming, on the layer of material which can be selectively eliminated, a thin silicon layer 3 from 1 nm to 50 nm thick which also preferably ensures lattice continuity with the material that can be selectively eliminated and consequently with the silicon substrate;
forming a thin gate dielectric layer 4 on the thin silicon layer 3;
forming a gate 7 on the thin gate dielectric layer 4;
etching the thin gate dielectric layer 4, the thin silicon layer 3, the layer of material that can be selectively eliminated, and an upper part of the substrate 1 along two opposite sides of the gate 7 to form voids;
partly or totally selectively laterally etching the layer of material that can be selectively eliminated to form a continuous cavity 2 or a discontinuous cavity, filled with air, the total length of which represents at least 70% of a predetermined minimum length of the channel region;
optionally, filling the cavity 2 or the cavities with a solid dielectric material; and
filling the voids with silicon and doping them to form the source and drain regions 5 and 6.
The source and drain regions 5 and 6 are preferably formed by epitaxial growth of silicon followed by ion implantation of dopants. Implantation is advantageously followed by annealing to activate the dopants implanted in the source and drain regions 5 and 6 selectively. The annealing is carried out for a short time period at a high temperature.
However, in the fabrication method described above, creating the cavity 2 after forming the gate 7 and before forming the source and drain regions 5 and 6 has drawbacks if the cavity 2 is to be left filled with air. This is because activating (annealing) the source and drain regions 5 and 6 exposes the cavity 2 to high temperatures. Exposing cavities filled with air to high annealing temperatures can degrade the cavities.
Forming a cavity filled with air after activating the source and drain regions 5 and 6 may reduce the drawbacks of filling a cavity with air.
A method of fabricating a silicon on nothing (SON) structure semiconductor device in which the cavity filled with air has not been exposed to high temperatures during the step of activating the source and drain regions is described.
A method of fabricating an SON structure semiconductor device may include:
forming, on a main surface of a silicon substrate, a stack of layers including at least one combination of two layers having a bottom layer of germanium, or germanium and silicon alloy, and a top layer of silicon. If it has more than one combination of two layers, the stack of layers may include a first combination immediately adjacent the substrate and a final combination farthest away from the substrate;
forming, on the top silicon layer of the combination or the last combination of the stack, a thin gate dielectric layer and a gate;
forming source and drain regions along two opposite sides of the gate in the thin gate dielectric layer and in the stack;
etching at least one hole in the stack at least as far as the bottom germanium (or germanium and silicon alloy) layer of the combination or the first combination of the stack;
selectively laterally etching via the hole at least a part of the germanium (or germanium and silicon alloy) layer or layers of the stack to form a tunnel or tunnels under the gate; and
optionally internally passivating or filling the tunnel or tunnels with a dielectric material.
In other words, the source and drain regions are formed first while the germanium (or germanium and silicon alloy) layers that can be selectively eliminated are present. It is only after forming the source and drain regions that the material which can be selectively eliminated is etched, via the hole, to form the tunnel(s) (i.e., a cavity or cavities filled with air).
In one embodiment, the hole is etched by forming at least one vertical hole through the gate, the thin gate dielectric layer and the stack 15, and under the gate as far as the bottom germanium or germanium and silicon alloy layer of the first combination. It will be clear to the skilled person that several holes can be formed through the gate if the dimensions of the gate allow this.
In another embodiment, at least two vertical holes are etched through the source and drain regions as far as the germanium or germanium and silicon alloy layer of the first combination. As before, it will be clear to the skilled person that several holes can be formed in each region if the dimensions of the source and drain regions allow this. This variant can be used to fabricate devices requiring a gate with small dimensions. Etching holes in the gate is more suitable for devices such as sensors in which the gate can have large dimensions.
The source and drain regions can generally be formed by implanting dopants which diffuse under a part of the gate.
Spacers can be formed on two opposite lateral sides of the gate after forming it, in the conventional way. Forming such spacers is well known to the skilled person.
The source and drain regions can be formed in the conventional way by creating voids in the stack and extending as far as the substrate along two opposite sides of the gate, filling the voids with epitaxially grown silicon and then implanting dopants. However, the source and drain regions are preferably formed by implanting dopants in the stack and as far as the substrate after forming the gate (flanked with spacers) and without creating voids.
Dopants are implanted so that, by lateral diffusion, the doped areas (the source and drain regions) underlie the spacers and a portion of the gate.
The hole(s) to be used for lateral etching of the germanium or germanium and silicon alloy layer(s) can be made by a conventional etching process, for example, anisotropic plasma etching.
The germanium or SiGe alloy layers can be selectively laterally etched via one or more holes using a conventional process such as plasma etching or selective chemical etching using an oxidizing solution, which is well known in the art.
The selective lateral etching of the germanium or germanium and silicon alloy layer(s) via a hole is preferably controlled to form a tunnel or tunnels extending under the spacers. For example, the etching may be controlled by adjusting the parameters of the etching process, in particular the selective lateral etching temperature and time.
Before etching the hole, the entire device is preferably covered with a layer of passivating material.